1. Field of the Invention
The present invention relates to an LSI apparatus operated by an optical clock, particularly, to an LSI apparatus operated by an optical clock, in which a clock is optically distributed to an LSI chip for processing a signal at a high speed so as to convert the optical clock into an electric clock for operating the LSI.
2. Description of the Related Art
With improvement of the performance of an electronic device such as a bipolar transistor or an electric field effect transistor (FET), the operating speed of the large scale integration circuit (LSI) has been drastically improved in recent years. However, the improvement in the performance of the LSI, which is achieved by the miniaturization of the transistors, is accompanied by a serious problem. Specifically, the electric wiring for connecting the miniaturized transistors to each other has also been miniaturized so as to increase the wiring resistance and the capacitance between adjacent wirings. The increase in the capacitance between adjacent wirings, which poses a serious problem, now provides a bottle neck in respect of the further improvement in the performance of the LSI. The particularly serious problem resides in the distribution of the clocks to the internal circuit parts of the LSI. To be more specific, the reaching time of the clock signal differs depending on the arranging position of the LSI circuit part so as to make it difficult to achieve the operation in synchronism with the logic circuit. The particular problem is being made more and more serious in recent years.
In view of the above-noted problem in respect of the electric wiring, several ideas are proposed in, for example, Japanese Patent Disclosure (Kokai) No. 6-132516 in respect of the optical wiring LSI for optically connecting the inner regions of the LSI. It should be noted that the optical wiring permits easily achieving the wiring capable of distributing signals at scores of Gbps from the direct current because the optical wiring is substantially free from the dependency of the loss on the frequency under the frequency not more than 100 GHz and the wiring path is free from the electromagnetic interference. Also, as a method for simplifying the amplifying circuit on the photo-detector side and for suppressing the jitter of the distributed clock signals, a method for receiving two short optical pulse trains by using two photodiodes that are connected in series is disclosed in, for example, “IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 9, NO. 2, MARCH/APRIL 2003, PP. 400-409”.
In the distributing method of the optical clock signals disclosed in the literature quoted above, however, it is necessary to distribute individually the two short optical pulses, which are hereinafter referred to as “set pulse” and “reset pulse”. Also, in the system using the clock distributing tree, which is disclosed in the Japanese Patent document quoted above, the optical pulses are distributed through a large number of branched portions, with the result that it is difficult to align the wiring length and the light amount thereof for the set pulse and the reset pulse. It follows that the dependency on the site such that the reaching timing of the set pulse and the reset pulse differs depending on the site is not negligible, with the result that the clock jitter is substantially generated in the entire LSI system. It should also be noted that a bias drift is generated in the clock signal by the difference in the light amount between the set pulse and the reset pulse so as to give rise to the problem that the jitter is substantially increased by the warp in the width of the clock pulse or the change thereof.